In the deep-submicron era of semiconductor technology, shallow trench isolation (STI) is widely used for the isolation between active areas of semiconductor devices such as metal-oxide-semiconductor (MOS) transistors. Generally, the STI process includes: forming a shallow trench in the semiconductor substrate by, e.g., etching, for the isolation between the active areas in the semiconductor substrate; then, filling the shallow trench with dielectric material such that the dielectric fills up the shallow trench and extends to cover the surface of the semiconductor substrate; and finally, planarizing the dielectric such that the surface of the semiconductor substrate is exposed. The planarization method may be chemical-mechanical polishing. When the STIs are formed, semiconductor devices such as MOS transistors can be formed on the active areas between the STIs.
As shown in FIG. 1, conventional STI includes: a semiconductor substrate 10; shallow trenches formed in the semiconductor substrate 10, which are filled with a dielectric layer 11; and active areas in the semiconductor substrate 10 between the shallow trenches, where semiconductor devices, such as MOS transistors each with a gate, a source, and a drain, are formed. However, due to the planarization process and subsequent procedures such as cleaning, in the conventional STI structure, a recess 12 known as “divot” may be induced between the surface of the dielectric layer 11 and the adjacent surface of the semiconductor substrate 10. The divot may cause problems such as leakage and device performance degradation. Moreover, as the sizes of devices shrink, the divot's relative size compared with the device formed between the STI becomes larger, resulting in even more device performance degradation.